The present invention relates to a programmable logic device such as a field programmable gate array, and more particularly to a programmable cell included in a programmable logic device and a configuration of an interconnection network.
A programmable device or a programmable logic LSI such as a field programmable gate array has, in its inside, informations about configuration which specifies a hardware configuration, so that in accordance with the configuration information, a desired hardware is realized. In recent years, the hardware scale realizable by the programmable device has been on the increase as semiconductor fabrication techniques have been progressed. In this circumstance, in place of the gate array LSI, the programmable device has received a great deal of attention.
The programmable device may be classified into the following two typical types. The first type programmable device is disclosed in U.S. Pat. No. 4,870,302 issued to Xilinx and its re-issued Pat. No. 34,363 entitled "Configurable Electrical Circuit Having Configurable Logic Elements and Configurable Interconnections".
The second type programmable device is disclosed in U.S. Pat. No. 5,583,450 issued to Xilinx entitled "Sequencer For A Time Multiplexed Programmable Logic Device", and disclosed in U.S. Pat. No. 5,600,263 entitled "Configuration Modes For A Time Multiplexed Programmable Logic Device", and also disclosed in U.S. Pat. No. 5,629,637 entitled "Method Of Time Multiplexing A Programmable Logic Device", as well as disclosed in U.S. Pat. No. 5,646,545 entitled "Time Multiplexed Programmable Logic Device".
The first type programmable device comprises a combination of programmable logic cells and programmable interconnection cells, wherein logic cells and interconnection cells make pairs to be arranged to form a two-dimensional array.
The second type programmable device has a plurality of configurable informations in the logic cells and the interconnection cells so that selection of one configurable information is changed over time to other configurable information in order to time-multiplex the first type programmable devices.
The above U.S. patents are silent on interconnections for switching the configurable information and also silent on the method of switching the configurable information. It is required that the configurable information and input information for logic operations in the logic cells are controlled for every one bit and interconnections are provided for individuals, for which reasons it is also required that the interconnections are connected and switching is controlled for every one bit of the configurable information.
In the programmable device, however, switching the configurable information generally needs changes of all bits, for which reason it is not required that interconnections are connected for every bits to control the switching of the configurable information. In the programmable device, generally, the configurable informations of all of the logic cells are switched to realize entirely different functions or the configurable informations of some logic cells are switched to realize partially different functions. It is rare that the configurable information of each logic cell is switched. Accordingly, if the interconnections are connected to each bit of the configurable informations and subsequent control to switching the configurable information in the logic cell unit, then a large number of the interconnections is required, resulting in an increased occupied area of the programmable device and also in an increased power consumption.
If control informations for controlling switching operations of the configurable informations are generated outside or inside of the programmable device, it takes a long time to enter the control informations into the individual logic cells. This means that the conventional programmable device needs a long arithmetic time for switching the configurable informations.
In the above circumstances, it had been required to develop a novel programmable device free from the above problem.